The present invention relates generally to the field of integrated circuit processing, and more particularly relates to a method of manufacturing chips having a multiplicity of gate oxide thicknesses and/or compositions.
For some years, there has been a demand in the semiconductor industry for system-on-chip devices. These devices incorporate multiple functions on a single chip. To achieve these functions, multiple transistor element types, each operated by a different power supply voltage, are mounted together. For example, some constructions include a peripheral region having I/O (Input/Output) device transistors that operate at a relatively high voltage, a step-down circuit to reduce the voltage, and a core region having logic device transistors that operate at a lower voltage.
Manufacturing reliable high-quality devices with both high and low voltage transistors has proved challenging. High and low voltage transistors are formed with gate dielectrics having differing thicknesses and/or compositions. Processes that form gate dielectrics can have a deliterious effects on previously formed gate dielectrics and their substrate interfaces. For example, growing a second gate dielectric can cause regrowth of a first gate oxide.
When oxides are grown in multiple stages, they have lower quality substrate interfaces as compared to oxides grown in a single stage. A low quality interface is characterized at least in one respect by having a large number of weak or dangling bonds. These bonds can cause hot carrier problems in the channel region and a phenomenon referred to as Negative Bias Temperature Instability (NBTI). NBTI primarily affects PMOS transistors and involves interface state generation and positive charge formation in the dielectric when a negative bias voltage is applied to the transistor. Over time, NBTI causes the threshold voltage of PMOS transistors to increase. Previous efforts to mitigate NBTI have included doping the substrate with fluorine, which diffuses to the interface where it reacts to passivate dangling bonds, and treating the substrate to replace hydrogen with deuterium. Deuterium binds more strongly to silicon than hydrogen. These efforts to reduce NBTI have met with limited success. There remains an unsatisfied need for processes of forming multi-gate chips that have high quality gate dielectrics and substrate interfaces, that are relatively unsusceptible to NBTI, and exhibit improved gate oxide integrity and immunity from process induced damage.
The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention relates to a method of manufacturing a multi-gate integrated circuit device. According to the method, a protective coating is employed that substantially prevents processes used to form a second gate dielectric from affecting a first gate dielectric. In an exemplary process, an oxide gate dielectric is grown for peripheral region transistors, and a protective coating is deposited over the peripheral region gate oxide. In one example, the protective coating is silicon nitride, however, other materials such as silicon carbide may be employed. The oxide and protective coating subsequently are etched from a core region, and then a second oxide gate dielectric is grown for core region transistors while the silicon nitride coating substantially prevents further oxide growth in the peripheral region. The protective coating can also prevent nitridation of the core region gate dielectric from affecting the peripheral region gate dielectric.
The nitridation prevention, according to one aspect of the present invention, may be of use in cases where there is only one gate oxide thickness, but for some reason, it is desired to not have any nitrogen incorporation in some transistors. For example, nitridation prevention may be utilized to improve noise performance, and may be useful in cases where high-speed digital circuits are integrated with analog applications. Avoiding nitridation also improves the plasma damage immunity of the thick oxide in a multi-gate process.
According to one aspect of the present invention, the formation of multiple, differing gate dielectrics is provided, wherein a formation of a second subsequently formed gate dielectric does not negatively impact an interface quality of a first gate dielectric. The method comprises forming a first gate dielectric over both a first and second region of a semiconductor substrate. A protective coating such as silicon nitride is then formed over the first gate dielectric, and the silicon nitride and the first gate dielectric are then removed in the second region. A second gate dielectric is then formed in the second region, wherein the protective coating prevents re-growth associated with the first gate dielectric to occur during the second gate dielectric formation. Control gates are then formed over the first and second gate dielectrics (either with or without protective coating removal) to form gate structures in the first and second regions, respectively.
According to another aspect of the present invention, the first gate dielectric and protective coating thereover are formed in the first region and the second gate dielectric is subsequently formed in the second region. The second gate dielectric is then subjected to a nitridation to thereby increase the dielectric constant thereof and decrease any potential boron diffusion therethrough. The nitridation of the second gate dielectric does not impact the first gate dielectric due to the protective coating thereover. The protective coating may subsequently be removed, if desired, followed by the formation of conductive control gates thereover.
According to still another aspect of the present invention, a multi-gate semiconductor device is disclosed. The device comprises one or more high voltage transistors having a first gate dielectric in a first region and one or more low voltage transistors having a second gate dielectric in a second region of the substrate. The first gate dielectric is different than the second gate dielectric and includes a layer of silicon nitride. In addition, the second gate dielectric may be nitrided independently of the first gate dielectric.